• A eight bit CPU with two registers A (accumulator) and B.

• Sixteen bit Program Counter (PC) and Data Pointer (DPTR).

• Eight bit Program Status Word (PSW).

• Thirty Two input output pins arranged in four ports: P0-P3.

• Oscillator and Clock circuits.

• Two Oscillators and Three interrupt sources.

• Eight bit Stack Pointer (SP).

• Internal ROM of 0 to 4K Bytes.

• Internal Ram of 128 Bytes.

• Two 16 Bit Timers/Counters, T0 and T1.

• Full duplex serial timer/counter: SBUF.

• Control Registers.

The 8051 microcontroller is packaged in an 40 pin DIP, with the full name and abbreviations for each port on the CPU.

The Oscillator and Clock

All circuits in 8051 are synchronised with the help of a clock. The XTAL1 and XTAL2 pins are provided to connect external oscillators to the chip. The manufacturers decide the maximum and minimum frequencies of the chip.

Program Counter and DPTR

• The Program Counter is an 16 Bit register that points to the memory location holding the current instruction to be executed. The PC can point to a location from 0000h to 0FFFh when addressing the internal memory, or 0h to FFFFh.

• The DPTR register is made up of 2, called DPH and DPT. This is used for memory access for internal and external code.

A and B registers

• 8051 has 34 registers general purpose registers. Two of them are A and B registers are part of the CPU Core.

• The other 32 are arranged in the internal RAM as a part of four banks - B0-B3 of eight registers each - R0 - R7.

• The A accumulator register is the most versatile register available, and is used many operations including arithmetic, logical, and integer multiplication. A is also used for data transfer between any external memory and 8051.

• The B register is used alongside the A register for multiplication and division, and is a general location where data is stored.

Program Status Word Register

• This register contains a number of flags required for the operation of the CPU. During execution, there is a requirement of flags for recording the outputs of certain instructions and making decisions based on those results. The result of such instructions are stored in 1 bit registers called flags.

• All the flags are conveniently grouped inside the Program Status Word Register, and the Power Control Register, abbreviated as PSW and PCON respectively.

• The PSW register contains four flags that are set during arithmetic operations, two flags that hold the number of the selected register bank, and one general purpose flag that user programs can set.

• One must note that the flags in PSW are user controllable and bit addressable. The math flags are affected by arithmetic operations as well.

• The four math flags held by PSW are Carry(CY), Auxiliary Carry(AC), Overflow(OV) and Parity(P) flags.

Internal RAM

The 8051 processor come with 128 bytes of in built memory. The memory is segmented as follows:

• The 32 registers are divided in banks of four - B0 - B3of eight registers each R0 - R7

• The area from 00h to 1Fh(32 locations) used as general purpose registers.

• The register banks can be accessed through two ways: Either by their memory address, or their number.
  • For accessing R4 of the B1 bank, I can simply use it’s name provided the bank is selected using the PSW flags RS1 and RS2.
  • Or, I can access the R4 of B1 by simply using it’s address 0C.

• The area from 20h to 2Fh is called a bit addressable area. Here, each location can either be accessed by bit or a full register can be accessed as a byte.
  • For example, if I try to access the location 23h as a byte, it will access the entire register. But, 23h is also the fourth bit of the 24H address.

• The general purpose area is above the bit area, from address 30h to 7Fh and can be accessed as a byte.

The Stack Pointer

• The stack is a location in the internal RAM used for efficient data storage and retrieval.

• The 8-bit stack pointer (SP) holds the internal RAM address of the topmost data in the stack. When new data is added to the stack, the pointer is incremented. When the stack is read, the pointer is decremented to access the next byte of data. This operation is commonly known as "push" and "pop".

• Upon reset, the SP is set to 07h for the 8051 microcontroller. The programmer can set the stack pointer as needed.

• The size of the stack is limited by the internal RAM. If the stack exceeds its limits, it can overwrite the general-purpose register banks, bit addressable area, and other parts of the RAM. To avoid conflicts with other areas of the internal RAM, it is often placed at a higher address.

Special Function Registers (SFR)

• Some 8051 internal registers can be accessed by either using their name (only for certain opcodes) or using addresses from 80h to FFh. These registers are often concerned with special instructions, and therefore are called special function registers.

• Some SFR registers are also bit addressable, just like the bit addressable area of internal RAM.

• Not all addresses between 80h to FFh are used for SFRs.

SFRs are named in certain opcodes by their functional names, such as A or TH0, and are referenced by other opcodes by their addresses, such as 0E0h or 8Ch. Note that any address used in the program must start with a number; thus address E0h for the A SFR begins with 0. Failure to use this number convention will result in an assembler error when the program is assembled.

The system designer is not limited to the 4K of ROM and 128 Bytes of RAM internally available in the 8051. The port configurations allow a connection of external EPROMs and RAMs of upto 64K (16 address lines) to the MCU.

A connection diagram is shown on the right. The 16 bit address lines are divided into two parts, the lower byte connected via a latch. Initially, the address for memory is sent through pins A0-A15, and the latch is enabled once the address has settled on external memory’s pins. This latch is enabled through the ALE pin. This free’s up the A0-A7 pins and allows them to be used as data lines.

When accessing EPROM, we set PSEN` to low once the latch has been set, to allow EPROM to write to the data lines. When trying to read or write to the RAM, the WR` and the RD` pins are set accordingly.

Interrupts may be generated by internal chip operations or provided by external sources. Any interrupt can cause the 8051 to perform a hardware call to an interrupt handling subroutine that is located at a predetermined (by the 8051 designers) absolute address in program memory

• Five interrupts are provided in the 8051.

• If two interrupts with the same priority occur at the same time, then they have the following ranking:
  1. IE0
  2. TF0
  3. IE1
  4. TF1
  5. Serial = R1 OR T1

The interrupt saves the PC of the program, which is running at the time the interrupt is serviced on the stack in internal RAM. A call is then done to the appropriate memory location. These locations are shown in the following table:

In Service Register (ISR)

• It keeps track of which interrupt is in service.

• Eight bit register, each bit indicates which interrupt is in service.

Priority Resolver (PR)

• It examines IRR, ISR and IMR, and determines which interrupt has maximum priority and sends it to the microcontroller.

Interrupt Request Register (IRR)

• It can take eight different interrupts, and the bit of the register is set to one if it receives the corresponding interrupt.

Interrupt Mask Register (IMR)

• It also has eight bits. If any of the bit is set to zero, then the corresponding interrupt is masked.

Control Logic

• It is directly connected to the INTA and INT pins of Microprocessor.

• It stores the vector addresses during ICW.

Cascade Butter Comparator

• Used to interface with slave/master 8259.

• SP/EN - In buffered mode, this pin can be used as an output to control buffer transceivers. In non buffered mode, it is used to designate if master(1) or slave(0).

Data Bus buffer

• Used to send Control, Status and Interrupt Vector information to the CPU.

Read Write Logic

• It takes inputs to RD, WR, A0 and CS.

• It holds the Initialisation Command Words(ICW) and Operation Command Words(OCW).

• A0 pin acts in conjunction with RD, CS and WR pins. It is used to decipher various command words the CPU writes and status that CPU wishes to read.

Operational Modes

There are two basic operational modes for 8255 IC:

• Bit Set/Reset Mode (BSR)

• Input/Output Mode

These two modes are selected on the basis of the D7 bit provided by the microcontroller. When D7 is 1, 8255 operates in I/O mode, and when D7 = 0, it operates in BSR mode.

Bit Set Reset Mode

• In this mode, each pin of port C can be set/reset by writing a suitable value to the control word register.

• D7 is always 0 for BSR. D6,5,4 are don’t care bits. D3,2,1 are port C bit select. Finally D0 is used to set/reset the particular pin.

• Eg: 0000 1011 will set PC_5 to 1.

I/O Mode

Mode 0:

Mode 1:

Mode 2:

• In this mode, A is used as a bidirectional mode, and five bits of port C is used for handshake. Interrupt logic is supported. Mode 2 is not available to port B.

• Inputs and outputs are latched.

• The five pins of port C are configured as follows:
  • INTR – The CPU is asked for the next data byte to/from it.
  • OBF(Output Buffer Full): When this signal becomes low, that means CPU has written data to the output port.
  • ACK(Acknowledge): This signal is given by an output device, confirms that the data has been transferred from the CPU to the output device. Now, the data bus can be tri stated and next data byte can be sent to port A.
  • (STB) Strobe Input: If this lines falls to logic low level, the data available at 8-bit input port is loaded into input latches.
  • Input Buffer Full (IBF): If this lines falls to logic low level, the data available at 8-bit input port is loaded into input latches. This can be used as an acknowledge that the data has been received by the receiver.
  • INTR – This active high output signal can be used to interrupt the CPU whenever an input device requests the service. INTR is set by a high STB pin and a high at IBF pin.
  • INTE is an internal flag that can be controlled by the bit set/reset mode of either PC4(INTEA) or PC2(INTEB).

• The INTEA and INTEB flags are controlled by the bit set-reset mode of PC6 and PC2 respectively.